Weekly Work Log - CW 2

8 Jan 2018

The purpose of the weekly work log posts is to report about my activities during the previous weeks.

Merged pull requests

Rust nix #799: My pull request got finally merged! This fixes various issues with the nix crate on DragonFly, as you can read in my commit message.
Rust pb #61: My pull request that fixes progress bar (pb) crate for FreeBSD and DragonFly has been merged. This should better be fixed directly in libc, but as this would be a breaking change, it is not accepted at the moment.
sass-rs #18: Fix build for BSDs.
Add cad/iverilog to Ravenports. Verilog is a hardware description language that can be used for instance to program FPGAs (or to generate ASICs).

I have been working on patching mrustc, which is an alternative Rust compiler written in C++, so that it works on DragonFly. My patches can be found here. I need to clean them up in order to open a pull request.
The Spectre and Meltdown vulnerabilities have been disclosed to public. I read both papers and upgraded my main system to be not exploitable for the Meltdown vulnerability (thanks to Matthew Dillon who wrote a patch within two days).
I hacked up a simple Forth interpreter in Rust, called ToyForth. Forth is a language that you can easily implement directly in assembly, while the language itself is quite powerful. My implementation compiles code into a simple virtual stack machine instruction set. Some sample code:

( Define a function SQUARES )
: SQUARE ( n -- n*n ) DUP * ;

( Execute function )
3 SQUARE . ( prints 9 )

I have been watching presentations by Ivan Godard about the Mill general-purpose CPU architecture. The Mill uses in-order execution and can issue up to 33 instructions in parallel using an intelligent VLIW architecture. Mainly the problem with VLIW (Very Long Instruction Word) is that of how to encode the instructions efficiently, as you don't want to use 132 bytes for a single instruction for various reasons. They filed lots of patents which were granted recently. Architecture-wise I think this is a big breakthrough, as our current out-of-order architectures (any modern CPU) use up a lot of power due to the huge amount of internal state (some 300 internal rename registers) they have to keep. The Mill pushes the data-flow analysis into the compiler in the veins of the Itanium architecture or DSP architectures.